Self-aligned enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment


Wide bandgap AlGaN/GaN high electron mobility transistors (HEMTs) are emerging as excellent candidates for high power, high frequency and also high temperature applications. Up to now, the focus has been to improve the performance of depletion-mode (D-mode) AlGaN/GaN HEMTs. From the application point of view, enhancement-mode (E-mode) HEMTs have many advantages. For applications such as high frequency PAs and LNAs, E-mode HEMTs allow elimination of negative-polarity voltage supply, thereby reducing the circuit complexity and cost. For digital applications, direct-coupled FET logic (DCFL) that features integration of D-mode and E-mode HEMTs offers the simplest circuit configuration. Several approaches, such as chloride-based ICP gate recess etching [1], [2] and gate metal (e.g. Pt) sunk into AlGaN cap layer by rapid thermal annealing [3], were used to achieve E-mode AlGaN/GaN HEMTs. However, the gate recess etching approach may encounter large gate leakage currents and the gate metal sinking process can only take effects on samples with near zero pinch off voltages. Here, we demonstrate a reliable technique to fabricate E-mode AlGaN/GaN HEMTs using a fluoride-based plasma treatment and post-gate rapid thermal annealing. The schematic cross section of E-mode AlGaN/GaN HEMT is shown in Fig. 1. Starting with a conventional D-mode AlGaN/GaN heterostructure sample, (electron sheet density 1.3x 1013 cm-2 and and mobility 1000 cm2/Vs), device mesa was etched using C12/He plasma dry etching followed by source/drain ohmic contact formation with Ti/Al/Ni/Au annealed at 850'C for 45 seconds. After gate windows with 1 gm length were opened by contact photolithography, the sample was treated by CF4 plasma in an RIE system at an RF plasma power of 150W for 150 sec. Ni/Au e-beam evaporation and lift-off were carried out subsequently to form the gate electrodes. The plasma treated gate region and the gate electrode were self-aligned. Post-gate rapid thermal annealing (RTA) was conducted at 400 °C for lOmins. The devices have a source-gate spacing of Lsg = I um and a gate-drain spacing of Lgd = 2 um. D-mode HEMTs were also fabricated on the same sample without plasma treatment to the gate region. Figure 2 shows the transfer characteristics of both D-mode and E-mode AlGaN/GaN HEMTs. Defining V,h as the gate bias intercept of the linear extrapolation of drain current at the point of peak transconductance (g) the V,h of E-mode device was determined to be 0.9 V, while the V1h of D-mode device is 4.0 V. At Vgs = OV, the transconductance reaches zero, indicating a true enhancement-mode operation. The drain current is well pinched off and shows a leakage of 28 gA/mm at Vd, = 6 V, the smallest value reported to date for E-mode AlGaN/GaN HEMTs. The peak gm, is 151 mS/mm for the D-mode HEMT and 148 mS/mm for the E-mode HEMT, respectively. The maximum drain current ('max) reaches 313mA/mm at a gate bias (Vgs) of 3V. Figure 3 shows the output curves of the E-mode device before and after RTA process. No change in threshold voltage was observed after the RTA. Comparison of the current-voltage (I-V) characteristics of E-mode device before and after RTA suggests that post-gate RTA plays a key role in recovering the damages induced during the plasma treatment. The fabricated E-mode AlGaN/GaN HEMT showed an fT of 10.1 GHz and an frnax of 34.3 GHz, a little lower than that of its D-mode counterpart, whose fT andfgax were 13.1 GHz and 37.1 GHz, respectively. In conclusion, we demonstrated a simple self-aligned method to fabricate high-performance E-mode HEMTs with low on-resistance and low knee voltages, which are required for single-polarity supply voltage amplifiers and integrated digital circuits.


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